Newer
Older
Multi-StageDesignTool / AlgebraicDataflowArchitectureModel / models / Clock.dtram
Okina-kina on 15 Mar 705 bytes firsr commit
model {
	channel CIO1 {
	   out min(m: Double, tick) == mod(m + 1, 60)
	}
	channel Clock {
	   in min(m, update(m2)) == m2
	   out hour(h: Double, update(m2)) == if(eq(m2, 0), mod(h + 1, 24), h)
	}
	channel MinUpdate {
	   in min(m, update(m2)) == m2
	   out min_ang(m_ang: Double, update(m2)) == m2 / 30 * PI
	}
	channel HourUpdate {
	   in hour(h, update(h2)) == h2
	   out hour_ang(h_ang: Double, update(h2)) == h2 / 6 * PI
	}
}
geometry {
    node c HourUpdate:520,340,30,30
    node c MinUpdate:520,100,30,30
    node c Clock:280,220,30,30
    node r min_ang:670,100,80,30
    node r min:250,100,80,30
    node r hour:270,340,80,30
    node r hour_ang:680,340,80,30
    node ioc CIO1:100,100,30,30
}